module Control(
  Instruction,
  RegDst,
  Jump,
  Branch,
  MemRead,
  MemtoReg,
  ALUOp,
  MemWrite,
  ALUSrc,
  RegWrite
);
input [5:0]Instruction;
output RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite;
output [2:0]ALUOp;


and regdst(RegDst, ~Instruction[0], ~Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], ~Instruction[5]);

wire RegWrite1, RegWrite2;
and regwrite1(RegWrite1, ~Instruction[0], ~Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], ~Instruction[5]);
and regwrite2(RegWrite2, ~Instruction[3], ~Instruction[4], Instruction[5]);
or regwrite(RegWrite, RegWrite1, RegWrite2);

nand alusrc(ALUSrc, ~Instruction[0], ~Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], ~Instruction[5]);

and memwrite(MemWrite, Instruction[0], Instruction[1], ~Instruction[2], Instruction[3], ~Instruction[4], Instruction[5]);

and memread(MemRead, Instruction[0], Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);

and memtoreg(MemtoReg, Instruction[0], Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);

and branch(Branch, ~Instruction[0], ~Instruction[1], Instruction[2], ~Instruction[3], ~Instruction[4], ~Instruction[5]);

and jump(Jump, ~Instruction[0], Instruction[1], Instruction[2], ~Instruction[3], ~Instruction[4], ~Instruction[5]);

wire [2:0]lwswt;
nand lwswt0(lwswt[0], ~Instruction[4], Instruction[5]);
and lwswt1(lwswt[1], ~Instruction[4], Instruction[5]);
nand lwswt2(lwswt[2], ~Instruction[4], Instruction[5]);

wire [2:0]beqt;
nand beqt0(beqt[0], ~Instruction[0], ~Instruction[1], Instruction[2], ~Instruction[3], ~Instruction[4], ~Instruction[5]);
and beqt1(beqt[1], ~Instruction[0], ~Instruction[1], Instruction[2], ~Instruction[3], ~Instruction[4], ~Instruction[5]);
and beqt2(beqt[2], ~Instruction[0], ~Instruction[1], Instruction[2], ~Instruction[3], ~Instruction[4], ~Instruction[5]);

or out0(ALUOp[0], lwswt[0], beqt[0]);
or out1(ALUOp[1], lwswt[1], beqt[1]);
or out2(ALUOp[2], lwswt[2], beqt[2]);

endmodule

module ALUcontrol(
  ALUOp,
  Instruction,
  ALUcon
);

input [2:0]ALUOp;
input [5:0]Instruction;
output [2:0]ALUcon;

wire [2:0]andt;
nand andt0(andt[0], ~ALUOp[0], ~ALUOp[1], ALUOp[2], ~Instruction[0], ~Instruction[1], Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);
nand andt1(andt[1], ~ALUOp[0], ~ALUOp[1], ALUOp[2], ~Instruction[0], ~Instruction[1], Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);
nand andt2(andt[2], ~ALUOp[0], ~ALUOp[1], ALUOp[2], ~Instruction[0], ~Instruction[1], Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);

wire [2:0]ort;
and ort0(ort[0], ~ALUOp[0], ~ALUOp[1], ALUOp[2], Instruction[0], ~Instruction[1], Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);
nand ort1(ort[1], ~ALUOp[0], ~ALUOp[1], ALUOp[2], Instruction[0], ~Instruction[1], Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);
nand ort2(ort[2], ~ALUOp[0], ~ALUOp[1], ALUOp[2], Instruction[0], ~Instruction[1], Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);

wire [2:0]addt;
nand addt0(addt[0], ~ALUOp[0], ~ALUOp[1], ALUOp[2], ~Instruction[0], ~Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);
and addt1(addt[1], ~ALUOp[0], ~ALUOp[1], ALUOp[2], ~Instruction[0], ~Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);
nand addt2(addt[2], ~ALUOp[0], ~ALUOp[1], ALUOp[2], ~Instruction[0], ~Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);

wire [2:0]subt;
nand subt0(subt[0], ~ALUOp[0], ~ALUOp[1], ALUOp[2], ~Instruction[0], Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);
and subt1(subt[1], ~ALUOp[0], ~ALUOp[1], ALUOp[2], ~Instruction[0], Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);
and subt2(subt[2], ~ALUOp[0], ~ALUOp[1], ALUOp[2], ~Instruction[0], Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);

wire [2:0]sltt;
and sltt0(sltt[0], ~ALUOp[0], ~ALUOp[1], ALUOp[2], ~Instruction[0], Instruction[1], ~Instruction[2], Instruction[3], ~Instruction[4], Instruction[5]);
and sltt1(sltt[1], ~ALUOp[0], ~ALUOp[1], ALUOp[2], ~Instruction[0], Instruction[1], ~Instruction[2], Instruction[3], ~Instruction[4], Instruction[5]);
and sltt2(sltt[2], ~ALUOp[0], ~ALUOp[1], ALUOp[2], ~Instruction[0], Instruction[1], ~Instruction[2], Instruction[3], ~Instruction[4], Instruction[5]);

wire [2:0]lwswt;
nand lwswt0(lwswt[0], ~ALUOp[0], ALUOp[1], ~ALUOp[2]);
and lwswt1(lwswt[1], ~ALUOp[0], ALUOp[1], ~ALUOp[2]);
nand lwswt2(lwswt[2], ~ALUOp[0], ALUOp[1], ~ALUOp[2]);

wire [2:0]beqt;
nand beqt0(beqt[0], ~ALUOp[0], ALUOp[1], ALUOp[2]);
and beqt1(beqt[1], ~ALUOp[0], ALUOp[1], ALUOp[2]);
and beqt2(beqt[2], ~ALUOp[0], ALUOp[1], ALUOp[2]);


or out0(ALUcon[0], andt[0], ort[0], addt[0], subt[0], sltt[0], lwswt[0], beqt[0]);
or out1(ALUcon[1], andt[1], ort[1], addt[1], subt[1], sltt[1], lwswt[1], beqt[1]);
or out2(ALUcon[2], andt[2], ort[2], addt[2], subt[2], sltt[2], lwswt[2], beqt[2]);








endmodule